1. Field of the Invention
This invention relates to a semiconductor device, and more particularly, to a semiconductor device integrated with a Schottky diode.
2. Description of the Prior Art
A Schottky diode is a unipolar device using electrons as carriers. Since the carrier recombination is nearly eliminated, the switching speed of the Schottky diode is high. Moreover, in response to a low forward bias voltage (Vf), the Schottky diode has higher forward current and shorter reverse recovery time (tRR). And high-frequency signals produced by the Schottky diode can be turned-off quicker than conventional PN junction devices.
Please refer to FIGS. 1 and 2, which are schematic drawings illustrating a conventional semiconductor device integrated with Schottky diode at intermediate stages of fabrication. As shown in FIG. 1, the conventional semiconductor device integrated with Schottky diode 100 includes a substrate 102, a large opening area of n-well 104, a ring-shaped insulating layer 106, a metal silicide layer 108, a ring-shaped isolation structure 110, and an n-doped region 112 serving as the drain. As shown in FIGS. 1 and 2, the ring-shaped insulating layer 106 can be, for example a self-aligned silicide blocking (hereafter abbreviated as SAB) layer formed on the n-well 104 for defining regions where the metal silicide layer 108 to be formed, and the metal silicide layer 108 and the n-well 104 construct a Schottky diode.
It should be noted that other devices for constructing the integrated circuits (ICs) can be disposed on the substrate 102. For example, transistor devices are formed on the substrate 102. And an inter-layer dielectric (hereinafter abbreviated as ILD) layer 130 is formed on the substrate 102 after the devices required to be formed on the substrate 102 are fabricated. Thereafter, a planarization process is performed to remove superfluous dielectric layer to obtain a flat surface. However, as shown in FIG. 1, since Schottky diode is formed on the large opening area of n-well 104, device density of this given area is much lower than device densities of other area. Consequently, over-polishing issue, also known as dishing effect, is often found during the planarization process. And thus a recess 140 is formed on in the ILD layer 130 on the Schottky diode.
Furthermore, a replacement metal gate (hereinafter abbreviated as RMG) process may be performed after forming the ILD layer 130 if required. Accordingly, the planarization process is to further polish other layer(s) formed on the substrate 102, such as the contact etch stop layer (CESL) 124 and the hard mask layer/cap layer 122 which is used to protect the dummy gate 120. During this planarization process, the dishing effect is worsened: the metal silicide layer 108 may be damaged by this planarization process. It is well-known to those skilled in the art that, according to the RMG process, the dummy gate 120 is removed to form a gate trench (not shown), and followed by filling the gate trench with work function metal layer(s) and filling metal(s). Then, another planarization process is performed to remove superfluous metal material and thus a metal gate 150 is obtained. However, the metal material 152 is to be unavoidably remained in the recess 140 after the planarization process as shown in FIG. 2. And the metal material 152 remained in the recess 140 seriously causes adverse impacts to the following interconnection fabrication processes.
It is therefore concluded that the semiconductor device integrated with Schottky diode faces difficulties in the fabrication processes, it even renders adverse impacts to IC reliability. Consequently, a semiconductor with Schottky diode which is able to avoid the abovementioned dishing effect is still in need.